When a liquid crystal panel is driven by alternating driving in an active matrix type liquid crystal display device adopting a point-at-a-time method, a data signal line is pre-charged before a pixel is supplied with a video signal via the data signal line, so that each pixel is stably charged to a predetermined charge amount. In this arrangement, when the pre-charging is carried out with respect to all data signal lines at the same time, the power source for pre-charging is required to have high driving ability so as to deal with large writing amount for all data signal lines. Some pre-charging systems have been introduced as technologies to solve this problem by carrying out pre-charging with respect to a small group of the data signal lines.
For example, Japanese Laid-Open Patent Application Tokukaihei 07-295520/1995 published on Nov. 10, 1995 (corresponding to U.S. Pat. No. 5,686,936 issued on Nov. 11, 1997; hereinafter referred to as a patent document 1) discloses such an arrangement that, when a video signal is supplied to a data signal line, the sampling signal of the video signal outputted from a shift register of the data signal line driver turns on a switch of another data signal line, so as to carry out pre-charging of the data signal line from a pre-charging power source through the switch.
Further, Japanese Laid-Open Patent Application Tokukai 2000-89194/2000 published on Mar. 31, 2000 (corresponding to European patent publication No. EP0984423A2 issued on Mar. 8, 2000; hereinafter referred to as a patent document 2) discloses an arrangement of dividing the data signal lines into some blocks so that each block includes several number of data signal lines. In this arrangement, when a video signal is supplied to the n-th data signal line block from the data signal line driver, the sampling signal of the video signal carries out pre-charging of the n+1th data signal line block from a pre-charging power source.
Further, Japanese Laid-Open Patent Application Tokukai 2000-206491/2000 published on Jul. 28, 2000 (hereinafter referred to as a patent document 3) discloses an arrangement of using transfer pulse input of a transfer stage of the data signal line driver as a timing pulse for opening/closing an analog switch for carrying out pre-charging of the data signal line in the transfer stage, and also delaying the transfer pulse input to be later than the timing pulse for pre-charging, so as to use the input as a timing pulse for opening/closing an analog switch used for supplying actual data (video signal) to the data signal line. In this arrangement, the transfer pulse output of the transfer stage becomes a transfer pulse input of the next transfer stage, and this input is used as a timing pulse for carrying out pre-charging of the next stage transfer stage, and also used as a timing pulse of the output of actual data.
The data signal line drivers of foregoing arrangements use a switch having a capacitive control terminal of such as a MOSFET including a TFT (for example, a gate), in each data signal line. Also, the pre-charging voltage of the control terminal is controlled to be used for operating the switch between a conductive state and a non-conductive state in a point-at-a-time method. Upon its output, the control signal (for example, a gate signal) for operating the switch in a point-at-a-time method is normally shifted in a horizontal direction by a shift register made up of plural stages flip-flops. Further, another similar switch operated between a conductive state and a non-conductive state by a point-at-a-time method is additionally provided so as to carry out pre-charging of the data signal line.
Further, the foregoing arrangements disclosed in those publications can realize reduction in area of the pre-charging circuit. For example, the pre-charging circuit is provided inside of the data signal line driver for the purpose of providing a sufficient frame area of the liquid crystal display device.
Note that, Japanese Laid-Open Patent Application Tokukai 2001-135093 published on May 18, 2001 (has also been applied to US Patent Office with the application Ser. No. of 09/703,918; hereinafter referred to as a patent document 4), which is made prior to the present application by the same applicant as that of the present invention, discloses a configuration in which a switch circuit receives a clock signal outputted from the respective set-reset flip-flops of the shift register, and the received signal is used as a set signal of the next stage set-reset flip-flop. On the other hand, the present embodiment introduces a totally new idea such that a received clock signal is used as a control signal for carrying out pre-charging of the data signal line, and the pre-charging potential is supplied to a switch connected to the data signal line. Further, Japanese Laid-Open Patent Application Tokukai 2001-307495 published on Nov. 2, 2001 (has also been applied to US Patent Office with the application Ser. No. of 09/703,918; hereinafter referred to as a patent document 5), and Japanese Laid-Open Patent Application Tokukai 2000-339985 published on Dec. 8, 2000 (has also been applied to US Patent Office with the application Ser. No. of 09/578,440; hereinafter referred to as a patent document 6), which are made prior to the present application by the same applicant as that of the present invention, disclose a configuration of carrying out level shift of a received clock signal which is outputted from the respective set-reset flip-flop constituting the shift register, so as to use the clock signal as a set signal of the next stage set-reset flip-flop. On the other hand, the present embodiment introduces a totally new idea such that the control signal for carrying out pre-charging of the data signal line is generated by subjecting the clock signal to level shift, and the pre-charging potential is supplied to a switch connected to the data signal line.
However, the data signal line drivers disclosed in the patent document 1 and the patent document 2 use only one circuit for supplying a control signal for operating the switch between the conduction state and the non-conduction state so as to output a video signal to a data signal line, and also for supplying another control signal used for controlling a different switch between the conduction state and the non-conduction state so as to carry out pre-charging of another data signal line. In this arrangement, when pre-charging is carried out in alternating driving, the foregoing switching operation brings about a powerful charging current of an impulse state since the pre-charging in the alternating driving is carried out by powerfully changing the potential (almost inverting the polarity) of the data signal line and the pixel capacitance with respect to the potential in the previous sampling of the video signal. Since the control terminal of the switch is capacitive, a frequency component of this great charging current, which is relatively high, is transmitted to a control signal circuit of the switch via the capacitance of the control terminal, and therefore can fluctuate the potential of the control signal circuit, and may further fluctuate a video signal supplied to the data signal line via the control terminal of the switch for writing a video signal. Such fluctuation of the video signal causes such as a decrease of display uniformity, thereby degrading display quality.
On the other hand, the data signal line driver of the patent document 3 does not require the common use of the control signal circuits, and therefore the fluctuation of the video signal can be prevented; however, this arrangement requires a shift register for delaying the transfer pulse to be later than the timing pulse for pre-charging in addition to a shift register for transferring the transfer pulse, thus requiring a twice-scale shift register.
As has been explained, in case of carrying out pre-charging of a signal supplying line, such as a data signal line, with an internal pre-charging circuit by using a pre-charging power source having small driving ability, a conventional driver circuit of a display device such as a data signal line driver has failed to prevent fluctuation of a signal supplied to other signal supplying line while keeping the circuit scale of the shift register small. Note that, the patent documents 4 through 6 have no disclosures or suggestions regarding pre-charging.